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K7I643684M K7I641884M
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
72Mb DDRII SRAM Specification
165 FBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.3 March 2007
K7I643684M K7I641884M
Document Title
1Mx36-bit, 2Mx18-bit DDRII CIO b4 SRAM
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
Revision History
Rev. No. 0.0 0.1 History 1. Initial document. 1. Correct the JTAG ID register definition 2. Correct the AC timing parameter (delete the tKHKH Max value) 1. Add the Power-on Sequence specification 1. Correct the pin name table 1. Update the power consumption (Icc & Isb) 1. Finalize the datasheet 1. Add Pb-free comment 2. Change the Max. clock cycle time in AC TIMING CHARACTERISTICS 1. Correct the pin name table 1. Add Detail Specification of Power up Sequence Draft Date Mar. 9, 2003 Mar. 20, 2003 Remark Advance Preliminary
0.2 0.3 0.4 1.0 1.1
Aug. 16, 2004 Oct. 18, 2004 May. 17, 2005 Aug. 2, 2005 Jul. 6, 2006
Preliminary Preliminary Preliminary Final Final
1.2 1.3
Jan. 23, 2007 Mar. 5, 2007
Final Final
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Rev. 1.3 March 2007
K7I643684M K7I641884M
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
2Mx36-bit, 4Mx18-bit DDRII CIO b4 SRAM
FEATURES
* 1.8V+0.1V/-0.1V Power Supply. * DLL circuitry for wide output data valid window and future frequency scaling. * I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O. * Pipelined, double-data rate operation. * Common data input/output bus. * HSTL I/O * Full data coherency, providing most current data. * Synchronous pipeline read with self timed late write. * Registered address, control and data input/output. * DDR(Double Data Rate) Interface on read and write ports. * Fixed 4-bit burst for both read and write operation. * Clock-stop supports to reduce current. * Two input clocks(K and K) for accurate DDR timing at clock rising edges only. * Two input clocks for output data(C and C) to minimize clock-skew and flight-time mismatches. * Two echo clocks (CQ and CQ) to enhance output data traceability. * Single address bus. * Byte write function. * Simple depth expansion with no data contention. * Programmable output impedance. * JTAG 1149.1 compatible test access port. * 165FBGA(11x15 ball array FBGA) with body size of 15x17mm & Lead Free Org. Part Number K7I643684M-F(E)C(I)30 X36 K7I643684M-F(E)C(I)25 K7I643684M-FC(I)20 K7I643684M-FC(I)16 K7I641884M-F(E)C(I)30 X18 K7I641884M-F(E)C(I)25 K7I641884M-FC(I)20 K7I641884M-FC(I)16 Cycle Access RoHS Unit Time Time Avail. 3.3 4.0 5.0 6.0 3.3 4.0 5.0 6.0 0.45 0.45 0.45 0.50 0.45 0.45 0.45 0.50 ns ns ns ns ns ns ns ns

* *

* *
* -F(E)C(I) F(E) [Package type]: E-Pb Free, F-Pb C(I) [Operating Temperature]: C-Commercial, I-Industrial
FUNCTIONAL BLOCK DIAGRAM
36 (or 18) DATA REG
36 (or 18) 19 (or 20) WRITE/READ DECODE WRITE DRIVER
OUTPUT SELECT
SENSE AMPS
LD R/W BWX
4(or 2)
CTRL LOGIC
2Mx36 (4Mx18) MEMORY ARRAY
72 (or 36)
72 (or 36)
OUTPUT DRIVER
ADDRESS A0,A1
19 (or 20) ADD REG
& BURST LOGIC
OUTPUT REG
36 (or 18)
DQ
CQ, CQ
K K C C
(Echo Clock out)
CLK GEN SELECT OUTPUT CONTROL
Notes: 1. Numbers in ( ) are for x18 device.
DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
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Rev. 1.3 March 2007
K7I643684M K7I641884M
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 NC/SA* DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 SA DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW1 BW0 SA1 VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI
PIN CONFIGURATIONS(TOP VIEW) K7I643684M(1Mx36)
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 144Mb. 2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35.
PIN NAME
SYMBOL K, K C, C CQ, CQ Doff SA0,SA1 SA DQ0-35 PIN NUMBERS 6B, 6A 6P, 6R 11A, 1A 1H 6C,7C 3A,9A,10A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R 2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F 11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L 3M,10M,11M,2N,3N,11N,3P,10P,11P 4A 8A 7B,7A,5A,5B 2H,10H 11H 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L, 4M-8M,4N,8N 10R 11R 2R 1R 2A,1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E, 1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K 1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P DESCRIPTION Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Burst Count Address Inputs Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input Reference Voltage Output Driver Impedance Control Input Power Supply (1.8 V) Output Power Supply (1.5V or 1.8V) Ground JTAG Test Mode Select JTAG Test Data Input JTAG Test Clock JTAG Test Data Output No Connect 3 2 1 NOTE
R/W LD BW0, BW1,BW2, BW3 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC
Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally.
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Rev. 1.3 March 2007
K7I643684M K7I641884M
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 SA DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 SA NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA1 VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI
PIN CONFIGURATIONS(TOP VIEW) K7I641884M(2Mx18)
Notes: 2. BW0 controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17.
PIN NAME
SYMBOL K, K C, C CQ, CQ Doff SA0,SA1 SA DQ0-17 R/W LD BW0, BW1 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC PIN NUMBERS 6B, 6A 6P, 6R 11A, 1A 1H 6C,7C 2A,3A,9A,10A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R 2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L 10M,3N,3P,11P 4A 8A 7B, 5A 2H,10H 11H 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N 10R 11R 2R 1R 7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,11D 1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G 1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L 1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P DESCRIPTION Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Burst Count Address Inputs Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input Reference Voltage Output Driver Impedance Control Input Power Supply (1.8 V) Output Power Supply (1.5V or 1.8V) Ground JTAG Test Mode Select JTAG Test Data Input JTAG Test Clock JTAG Test Data Output No Connect 3 2 1 NOTE
Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally.
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Rev. 1.3 March 2007
K7I643684M K7I641884M
GENERAL DESCRIPTION
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
The K7I643684M and K7I641884M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7I643684M and 4,194,304 words by 18 bits for K7I641884M. Address, data inputs, and all control signals are synchronized to the input clock (K or K). Normally data outputs are synchronized to output clocks (C and C), but when C and C are tied high, the data outputs are synchronized to the input clocks (K and K). Read data are referenced to echo clock (CQ or CQ) outputs. Read address and write address are registered on rising edges of the input K clocks. Common address bus is used to access address both for read and write operations. The internal burst counter is fixed to 4-bit sequential for both read and write operations. Synchronous pipeline read and late write enable high speed operations. Simple depth expansion is accomplished by using LD for port selection. Byte write operation is supported with BW0 and BW1 (BW2 and BW3) pins for x18 (x36) device. IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system. The K7I643684M and K7I641884M are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K. Address is presented and stored in the read address register synchronized with K clock. For 4-bit burst DDR operation, it will access four 36-bit or 18-bit data words with each read command. The first pipelined data is transferred out of the device triggered by C clock following next K clock rising edge. Next burst data is triggered by the rising edge of following C clock rising edge. Continuous read operations are initiated with K clock rising edge. And pipelined data are transferred out of device on every rising edge of both C and C clocks. In case C and C tied to high, output data are triggered by K and K instead of C and C. When the LD is disabled after a read operation, the K7I643684M and K7I641884M will first complete burst read operation before entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state.
Write Operations
Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K. Address is presented and stored in the write address register synchronized with next K clock. For 4-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command. The first "late writed" data is transferred and registered in to the device synchronous with next K clock rising edge. Next burst data is transferred and registered synchronous with following K clock rising edge. Continuous write operations are initiated with K rising edge. And "late writed" data is presented to the device on every rising edge of both K and K clocks. When the LD is disabled, the K7I643684M and K7I641884M will enter into deselect mode. The device disregards input data presented on the same cycle W disabled. The K7I643684M and K7I641884M support byte write operations. With activating BW0 or BW1 (BW2 or BW3) in write cycle, only one byte of input data is presented. In K7I641884M, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17. And in K7I643684M BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.
Single Clock Mode
K7I643684M and K7I641884M can be operated with the single clock pair K and K, instead of C or C for output clocks. To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high during operation. After power up, this device cant change to or from single clock mode. System flight time and clock skew could not be compensated in this mode.
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Rev. 1.3 March 2007
K7I643684M K7I641884M
Depth Expansion
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
Separate input and output ports enables easy depth expansion. Each port can be selected and deselected independently and read and write operation do not affect each other. Before chip deselected, all read and write pending operations are completed.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ). The value of RQ (within 15%) is five times the output impedance desired. For example, 250 resistor will give an output impedance of 50. Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
Echo clock operation
To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are synchronized with internal data output. Echo clocks run free during normal operation. The Echo clock is triggered by internal output clock signal, and transferred to external through same structures as output driver.
Clock Consideration
K7I643684M and K7I641884M utilizes internal DLL(Delay-Locked Loops) for maximum output data valid window. It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles. Circuitry automatically resets the DLL when absence of input clock is detected.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-down.
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Rev. 1.3 March 2007
K7I643684M K7I641884M
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
Detail Specification of Power-Up Sequence in DDRII SRAM
DDRII SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
* Power-Up Sequence
1. Apply power and keep Doff at low state (All other inputs may be undefined) - Apply VDD before VDDQ - Apply VDDQ before VREF or the same time with VREF 2. Just after the stable power and clock(K,K), take Doff to be high. 3. The additional 2048 cycles of clock input is required to lock the DLL after enabling DLL * Notes: If you want to tie up the Doff pin to High with unstable clock, then you must stop the clock for a few seconds (Min. 30ns) to reset the DLL after it become a stable clock status.
* DLL Constraints
1. DLL uses either K clock as its synchronizing input, the input should have low phase jitter which is specified as TK var. 2. The lower end of the frequency at which the DLL can operate is 120MHz. 3. If the incoming clock is unstable and the DLL is enabled, then the DLL may lock onto a wrong frequency and this may cause the failure in the initial stage.
Power up & Initialization Sequence (Doff pin controlled)
~ ~~
K,K
1024 cycle DLL Locking Range
Inputs Clock must be stable
Status
Power-Up
Unstable CLKstage
~ ~~
Any Command
VDD VDDQ VREF Doff
Power up & Initialization Sequence (Doff pin Fixed high, Clock controlled)
~~ ~
K,K
Min 30ns
~~
1024 cycle
~
~
Status VDD VDDQ VREF
Power-Up
Unstable CLKstage
~
Stop Clock
DLL Locking Range
Inputs Clock must be stable
Any Command
* Notes: When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 2048 cycles of clock input is needed to lock the DLL.
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Rev. 1.3 March 2007
K7I643684M K7I641884M
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
K Stopped LD X H L L R/W X X H L
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
Q Q(A0) Previous state High-Z QOUT at C(t+1) Din at K(t+1) Q(A1) Previous state High-Z QOUT at C(t+2) Din at K(t+1) Q(A2) Previous state High-Z QOUT at C(t+2) Din at K(t+2) Q(A3) Previous state High-Z QOUT at C(t+3) Din at K(t+2)
OPERATION Clock Stop No Operation Read Write
Notes: 1. X means "Dont Care". 2. The rising edge of clock is symbolized by (). 3. Before enter into clock stop status, all pending read and write operations will be completed.
WRITE TRUTH TABLE(x18)
K
Notes: 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (). 3. Assumes a WRITE cycle was initiated. 4. This table illustrates operation for x18 devices.
K
BW0 L L L L H H H H
BW1 L L H H L L H H
OPERATION WRITE ALL BYTEs (K ) WRITE ALL BYTEs (K ) WRITE BYTE 0 (K ) WRITE BYTE 0 (K ) WRITE BYTE 1 (K ) WRITE BYTE 1 (K ) WRITE NOTHING (K ) WRITE NOTHING (K )
WRITE TRUTH TABLE(x36)
K
Notes: 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ). 3. Assumes a WRITE cycle was initiated.
K
BW0 L L L L H H H H H H
BW1 L L H H L L H H H H
BW2 L L H H H H L L H H
BW3 L L H H H H L L H H
OPERATION WRITE ALL BYTEs (K ) WRITE ALL BYTEs (K ) WRITE BYTE 0 (K ) WRITE BYTE 0 (K ) WRITE BYTE 1 (K ) WRITE BYTE 1 (K ) WRITE BYTE 2 and BYTE 3 (K ) WRITE BYTE 2 and BYTE 3 (K ) WRITE NOTHING (K ) WRITE NOTHING (K )
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Rev. 1.3 March 2007
K7I643684M K7I641884M
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on VDD Supply Relative to VSS Voltage on VDDQ Supply Relative to VSS Voltage on Input Pin Relative to VSS Storage Temperature Operating Temperature (Commercial / Industrial) Storage Temperature Range Under Bias
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
SYMBOL VDD VDDQ VIN TSTG TOPR TBIAS RATING -0.5 to 2.9 -0.5 to VDD -0.5 to VDD+0.3 -65 to 150 0 to 70 / -40 to 85 -10 to 85 UNIT V V V C C C
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ must not exceed VDD during normal operation.
OPERATING CONDITIONS (0C TA 70C)
PARAMETER Supply Voltage Reference Voltage SYMBOL VDD VDDQ VREF MIN 1.7 1.4 0.68 MAX 1.9 1.9 0.95 UNIT V V V
DC ELECTRICAL CHARACTERISTICS(VDD=1.8V 0.1V, TA=0C to +70C)
PARAMETER Input Leakage Current Output Leakage Current SYMBOL IIL IOL TEST CONDITIONS VDD=Max ; VIN=VSS to VDDQ Output Disabled, -30 Operating Current (x36): QDR mode ICC VDD=Max, IOUT=0mA Cycle Time tKHKH Min -25 -20 -16 -30 Operating Current (x18): QDR mode ICC VDD=Max, IOUT=0mA Cycle Time tKHKH Min -25 -20 -16 Device deselected, IOUT=0mA, ISB1 f=Max, All Inputs0.2V or VDD-0.2V VOH1 VOL1 VOH2 VOL2 VIL VIH IOH=-1.0mA IOL=1.0mA -30 -25 -20 -16 MIN -2 -2 MAX +2 +2 900 800 700 650 850 750 650 600 400 380 360 340 V V V V V V 2,6 2,6 3 3 7,8 7,9 mA 1,5 mA 1,4 mA 1,4 UNIT NOTES A A
Standby Current(NOP): QDR mode
Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Input Low Voltage Input High Voltage
VDDQ/2-0.12 VDDQ/2+0.12 VDDQ/2-0.12 VDDQ/2+0.12 VDDQ-0.2 VSS -0.3 VREF+0.1 VDDQ 0.2 VREF-0.1 VDDQ+0.3
Notes: 1. Minimum cycle. IOUT=0mA. 2. |IOH|=(VDDQ/2)/(RQ/5)15% for 175 RQ 350. |IOL|=(VDDQ/2)/(RQ/5)15% for 175 RQ 350. 3. Minimum Impedance Mode when ZQ pin is connected to VDDQ. 4. Operating current is calculated with 50% read cycles and 50% write cycles. 5. Standby Current is only after all pending read and write burst operations are completed. 6. Programmable Impedance Mode. 7. These are DC test criteria. DC design criteria is VREF50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 8. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width 3ns). 9. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width 3ns).
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Rev. 1.3 March 2007
K7I643684M K7I641884M
PARAMETER Input High Voltage Input Low Voltage SYMBOL VIH (AC) VIL (AC)
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
MIN VREF + 0.2 MAX VREF - 0.2 UNIT V V NOTES 1,2 1,2
AC ELECTRICAL CHARACTERISTICS (VDD=1.8V 0.1V, TA=0C to +70C)
Notes: 1. This condition is for AC function test only, not for AC parameter test. 2. To maintain a valid level, the transition edge of the input must: a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC) b) Reach at least the target AC level c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
AC TIMING CHARACTERISTICS(VDD=1.8V0.1V, TA=0C to +70C)
PARAMETER Clock Clock Cycle Time (K, K, C, C) Clock Phase Jitter (K, K, C, C) Clock High Time (K, K, C, C) Clock Low Time (K, K, C, C)
Clock to Clock (K K, C C) Clock to data clock (K C, K C)
SYMBOL
-30 MIN 3.30 1.32 1.32 1.49 0.00 1024 30 0.45 -0.45 0.45 -0.45 0.27 -0.27 0.45 -0.45 0.40 0.40 0.30 0.40 0.40 0.30 -0.45 0.50 0.50 0.35 0.50 0.50 0.35 -0.30 -0.45 -0.45 1.45 MAX 8.40 0.20 1.60 1.60 1.80 0.00 1024 30 MIN 4.00
-25 MAX 8.40 0.20 2.00 2.00 2.20 1.80 0.00 1024 30 0.45 -0.45 0.45 -0.45 0.30 -0.35 0.45 -0.45 0.60 0.60 0.40 0.60 0.60 0.40 MIN 5.00
-20 MAX 8.40 0.20 2.40 2.40 2.70 2.30 0.00 1024 30 0.45 -0.50 0.45 -0.50 0.35 -0.40 0.45 -0.50 0.70 0.70 0.50 0.70 0.70 0.50 MIN 6.00
-16 MAX 8.40 0.20
UNIT NOTE
tKHKH tKC var tKHKL tKLKH tKHKH tKHCH tKC lock tKC reset tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCHQZ tCHQX1 tAVKH tIVKH tDVKH tKHAX tKHIX tKHDX
ns ns ns ns ns 5
2.80
ns cycle ns 6
DLL Lock Time (K, C) K Static to DLL reset Output Times C, C High to Output Valid C, C High to Output Hold C, C High to Echo Clock Valid C, C High to Echo Clock Hold CQ, CQ High to Output Valid CQ, CQ High to Output Hold C, High to Output High-Z C, High to Output Low-Z Setup Times Address valid to K rising edge Control inputs valid to K rising edge Data-in valid to K, K rising edge Hold Times K rising edge to address hold K rising edge to control inputs hold K, K rising edge to data-in hold
0.50 0.50 0.40 0.50
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3 3
7 7 3 3
2
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control singles are R, W,BW0,BW1 and BW2, BW3, also for x36 3. If C,C are tied high, K,K become the references for C,C timing parameters. 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. 5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable. 7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a 0.1 ns variation from echo clock to data. The data sheet parameters reflect tester guard bands and test setup variations.
- 11 -
Rev. 1.3 March 2007
K7I643684M K7I641884M
THERMAL RESISTANCE
PRMETER Junction to Ambient Junction to Case SYMBOL JA JC
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
TYP 21 2.48 Unit NOTES
C/W C/W
Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site thermal impedance. TJ=TA + PD x JA
PIN CAPACITANCE
PRMETER Address Control Input Capacitance Input and Output Capacitance Clock Capacitance SYMBOL CIN COUT CCLK TESTCONDITION VIN=0V VOUT=0V Typ 3.5 4 3 MAX 4 5 4 Unit pF pF pF NOTES
Note: 1. Parameters are tested with RQ=250 and VDDQ=1.5V.
2. Periodically sampled and not 100% tested.
AC TEST CONDITIONS
Parameter Core Power Supply Voltage Output Power Supply Voltage Input High/Low Level Input Reference Level Input Rise/Fall Time Output Timing Reference Level
Note: Parameters are tested with RQ=250
AC TEST OUTPUT LOAD
SymVDD VDDQ VIH/ VREF TR/TF Value 1.7~1.9 1.4~1.9 1.25/0.25 0.75 0.3/0.3 VDDQ/2 Unit V V V V ns V
VREF 0.75V
VDDQ/2 50 Zo=50
SRAM
ZQ 250
Overershoot Timing
20% tKHKH(MIN) VDDQ+0.5V VDDQ+0.25V VDDQ
Undershoot Timing
VIH
VSS VSS-0.25V VSS-0.5V
VIL
Note: For power-up, VIH VDDQ+0.3V and VDD 1.7V and VDDQ 1.4V t 200ms
20% tKHKH(MIN)
- 12 -
Rev. 1.3 March 2007
K7I643684M K7I641884M
APPLICATION INRORMATION
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
Vt R
DQ Address R W BW
SA
CQ CQ DQ R W BW0 BW1 C C K K
SRAM#1
ZQ R=250
R=250 CQ CQ DQ RW BW0 BW1 C C K K SRAM#4 ZQ ZQ
SA
R
Vt
MEMORY CONTROLLER
Return CLK Source CLK Return CLK Source CLK
Vt Vt
R=50 Vt=VREF
SRAM1 Input CQ SRAM1 Input CQ SRAM4 Input CQ SRAM4 Input CQ
- 13 -
Rev. 1.3 March 2007
K7I643684M K7I641884M
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
TIMING WAVE FORMS OF READ, WRITE AND NOP
NOP
READ (burst of 4)
READ (burst of 4)
NOP 5 6
NOP (Note3) 7
(burst of 4)
WRITE 8
(burst of 4)
READ
1
2
3
4
9
10
11
12
K
tKHKL tKHKH tKHKH
K
tIVKH tKLKH tKHIX
LD
R/W
SA
tAVKH
A0 tKHAX
A1
A2 tKHDX tDVKH
A3
DQ
tCHQV tKHCH tCHQX1
Q01
Q02
Q03
Q04
Q11
Q12
Q13
Q14
D21
D22
D23
D24
Q31
Q32
Q33
tCHQX
tCQHQX tCQHQV
tCHQZ
C C
tKHKH tKHKL tCQHQZ tKLKH tKHKH tCHCQH
CQ CQ
DONT CARE UNDEFINED
NOTE 1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc. 2. Outputs are disabled (High-Z) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent bus contention.
- 14 -
Rev. 1.3 March 2007
K7I643684M K7I641884M
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Instruction EXTEST IDCODE SAMPLE-Z RESERVED SAMPLE RESERVED RESERVED BYPASS TDO Output Boundary Scan Register Identification Register Boundary Scan Register Do Not Use Boundary Scan Register Do Not Use Do Not Use Bypass Register Notes 1 3 2 6 5 6 6 4
SRAM CORE
TDI
BYPASS Reg. Identification Reg. Instruction Reg. Control Signals
TDO
TMS TCK
TAP Controller
NOTE: 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use.
TAP Controller State Diagram
1 0 Test Logic Reset 0 Run Test Idle
1 1
Select DR 0 Capture DR 0 Shift DR 1 Exit1 DR 0 Pause DR 1 Exit2 DR 1 Update DR 0
1 1
Select IR 0 Capture IR
1
0
0 1 Shift IR 1 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 0
1
0 0
1
- 15 -
Rev. 1.3 March 2007
K7I643684M K7I641884M
SCAN REGISTER DEFINITION
Part 2Mx36 4Mx18 Instruction Register 3 bits 3 bits
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
Bypass Register 1 bit 1 bit ID Register 32 bits 32 bits Boundary Scan 109 bits 109 bits
ID REGISTER DEFINITION
Part 2Mx36 4Mx18 Revision Number (31:29) 000 000 Part Configuration (28:12) 00def0wx0t0q0b0s0 00def0wx0t0q0b0s0 Samsung JEDEC Code (11: 1) 00001001110 00001001110 Start Bit(0) 1 1
Note: Part Configuration /def=011 for 72Mb, /wx=11 for x36, 10 for x18. /t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O
BOUNDARY SCAN EXIT ORDER
ORDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PIN ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E ORDER 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PIN ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 PIN ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal
Note: 1. NC pins are read as "X" (i.e. dont care.)
- 16 -
Rev. 1.3 March 2007
K7I643684M K7I641884M
JTAG DC OPERATING CONDITIONS
Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage (IOH=-2mA) Output Low Voltage (IOL=2mA) Symbol VDD VIH VIL VOH VOL
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
Min 1.7 1.3 -0.3 1.4 VSS Typ 1.8 Max 1.9 VDD+0.3 0.5 VDD 0.4 Unit V V V V V Note
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level
Note: 1. See SRAM AC test output load on page 11.
Symbol VIH/VIL TR/TF
Min 1.3/0.5 1.0/1.0 0.9
Unit V ns V
Note
1
JTAG AC Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV Min 50 20 20 5 5 5 5 5 5 0 Max 10 Unit ns ns ns ns ns ns ns ns ns ns Note
JTAG TIMING DIAGRAM
TCK
tCHCH tMVCH tCHMX
tCHCL
tCLCH
TMS
tDVCH tCHDX
TDI
tSVCH tCHSX
PI (SRAM)
tCLQV
TDO
- 17 -
Rev. 1.3 March 2007
K7I643684M K7I641884M
165 FBGA PACKAGE DIMENSIONS
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
B
Top View
A C D
A G
Side View
E
B
F
Bottom View
H
E
Symbol A B C D
Value 15 0.1 17 0.1 1.3 0.1 0.35 0.05
Units mm mm mm mm
Note
Symbol E F G H
Value 1.0 14.0 10.0 0.5 0.05
Units mm mm mm mm
Note
- 18 -
Rev. 1.3 March 2007

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